1. Field of the Invention
The present invention relates to the forming of capacitors of metal-insulator-metal type (MIM) in metallization levels of interconnection of semiconductor circuits.
2. Discussion of the Related Art
Capacitors having a capacitance on the order of from 5 to 50 fF/μm2 are more and more often directly formed in the metallization interconnect levels of the semiconductor circuits with which they are associated, rather than outside of such circuits. Such capacitors are intended to filter a signal with respect to a power supply, to form filters, to form an analog-to-digital converter, to form a voltage-controlled oscillator, or in radio-frequency applications. Such MIM capacitors may also be used as a memory point of memory devices.
FIGS. 1, 2, 3, and 4 illustrate different steps of manufacturing of a capacitor according to a known method. FIG. 1 is a cross-section view. FIG. 2 is a top view. FIG. 3 is an enlarged view of a portion of FIG. 1. FIG. 4 is a cross-section view at a step subsequent to those illustrated in FIG. 1.
As illustrated in FIG. 1, the capacitor-forming method starts with the forming, in a first thick interlevel dielectric layer 1, of a metal electrode 3. A second thick interlevel dielectric layer 5 is deposited over layer 1 and electrode 3 altogether. Layer 5 is generally formed of a first relatively thin insulating sub-layer 51 and of a thick layer 52 of an insulator that may be selectively etched with respect to first sub-layer 51. Sub-layer 51 is itself selectively etchable with respect to underlying layer 1. Typically, sub-layer 51 is a silicon nitride sub-layer (Si3N4) while layer 1 and sub-layer 52 are made of silicon oxide (SiO2). Then, layer 5 is selectively opened to expose first electrode 3 according to a predetermined pattern. For example, as illustrated in the top view of FIG. 2, parallel trenches 21 are dug into layer 5, five trenches of which are shown in cross-section view in FIG. 1 and in top view in FIG. 2. Trenches 21 are interconnected by a common perpendicular trench 22. Then, trenches 21, 22 are filled by successive conformal depositions of a thin metal layer 7, of an interelectrode insulator 8, of another thin metal layer 9. A conductive layer 11 fills trenches 21 and 22. Thin layer 7 is intended to increase the surface area of electrode 3 across the thickness of interlevel layer 5. Layer 11 is generally formed of polysilicon, of copper, of a copper-based alloy or any other conductive material.
FIG. 3 illustrates an enlarged cross-section view of FIG. 1 at the level of a trench 21 (FIG. 2). Conductive layers 7 and 9 are generally formed of respective sub-layers 71, 72 and 91, 92. Sub-layers 71 and 92 are generally identical and are intended to ensure a proper adherence between electrode sub-layers 72 and 91 and conductive layer 3 or 11, generally made of copper. Sub-layers 72 and 91, which are on either side of insulator 8 interposed between the electrodes, are also generally identical and are selected to ensure optimal electric performances. In particular, sub-layers 72 and 91 are selected to minimize the migration of the species forming them in the dielectric forming insulator 8. In addition, sub-layers 72 and 91 are selected to minimize the migration of the species forming insulator 8 in sub-layers 72 and 91. Typically, sub-layers 71, 72, 91, and 92 have a respective thickness of approximately 10 nm. Electrode sub- layers 71 and 92 are typically made of tantalum nitride (TaN). Sub-layers 72 and 91 are typically made of titanium nitride (TiN). Interelectrode dielectric 8 has an approximate thickness from 15 to 50 nm, for example, 30 nm, and is typically made of silicon nitride or tantalum oxide (Ta2O5).
After the depositions of layers 7, 8, 9, and 11, these layers are removed from the surface of layer 5 to only be kept in trenches 21 and 22 of FIG. 2. For this purpose, a chem.-mech. polishing, CMP, is generally performed.
At the next steps, as illustrated in the cross-section view of FIG. 4, a new interlevel dielectric layer 15 generally formed of a first thin sub-layer 151 typically made of silicon nitride and of a second thick sub-layer 152 typically made of silicon oxide is deposited over the entire structure.
The method then carries on with steps, not shown, aiming at completing the structure by the forming of contacts with lower electrode 3-7 and with upper electrode 9-11. It should be noted that an upper mechanical electrode 60 illustrated in dotted lines in FIG. 2 is frequently formed in layer 15.
A disadvantage of the above-described method lies in the fact that the resulting capacitors have relatively high leakage currents and this, randomly, between electrodes 9-11 and 7-3. Thus, the leakage currents for a 5-V voltage difference are greater than 10-6 A/cm2. Further, the capacitors have breakdown voltages randomly distributed across a wide range between 10 and 25 volts. Such variations are said to be random since these intervals not only appear between two capacitors formed in different wafers, but also between capacitors formed in a same wafer.